In a typical computing system, the power consumption associated with establishing and maintaining a peripheral component interconnect (PCI) express (PCIe) communications link between a processor circuit and a peripheral device such as a graphics card can be significant. Under circumstances in which limited power is available and the features of the PCIe peripheral are non-essential and/or may be performed by an integrated alternative device, it may be desirable to deactivate the PCIe peripheral and remove power from a PCIe controller and/or other circuitry supporting the PCIe link. For example, in systems in which the PCIe controller is integrated within the processor circuit, it may be desirable to remove power from the PCIe controller and/or other supporting circuitry in order to enable the processor circuit to enter a lower power state. However, according to conventional approaches, while an integrated PCIe controller may be disabled, no procedure is established by which an integrated PCIe controller can be powered down in the course of ongoing operation of a processor circuit within which it resides.